312 search results - page 55 / 63 » Architectural approaches to reduce leakage energy in caches |
100
click to vote
SENSYS
2006
ACM
15 years 5 months ago
2006
ACM
Sensor networks are fundamentally constrained by the difficulty and energy expense of delivering information from sensors to sink. Our work has focused on garnering additional si...
135
click to vote
ECRTS
2007
IEEE
15 years 6 months ago
2007
IEEE
Many embedded systems feature processors coupled with a small and fast scratchpad memory. To the difference with caches, allocation of data to scratchpad memory must be handled by...
IEEEPACT
2009
IEEE
15 years 6 months ago
2009
IEEE
—With increasing numbers of cores, future CMPs (Chip Multi-Processors) are likely to have a tiled architecture with a portion of shared L2 cache on each tile and a bankinterleave...
MICRO
1995
IEEE
15 years 3 months ago
1995
IEEE
Current superscalar processors, both RISC and CISC, require substantial instruction fetch and decode bandwidth to keep multiple functional units utilized. While CISC instructions ...
104
click to vote
RTSS
2008
IEEE
15 years 6 months ago
2008
IEEE
Wireless sensor networks (WSNs) have become an increasingly compelling platform for Structural Health Monitoring (SHM) applications, since they can be installed relatively inexpen...