218 search results - page 26 / 44 » Architecture Level Power-Performance Tradeoffs for Pipelined... |
ISCAS
2003
IEEE
15 years 2 months ago
2003
IEEE
Conventional ASIC designs are hard to be customized. Therefore DSP core-based ASIC design has potentially large payoff. This approach not only supports improved performance but al...
102
Voted
HPCA
2009
IEEE
15 years 10 months ago
2009
IEEE
Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce th...
DSD
2004
IEEE
15 years 1 months ago
2004
IEEE
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current Systemon-Chip design metho...
78
Voted
IPPS
2009
IEEE
15 years 4 months ago
2009
IEEE
DTA (Decoupled Threaded Architecture) is designed to exploit fine/medium grained Thread Level Parallelism (TLP) by using a distributed hardware scheduling unit and relying on exi...
DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
Retargetable C compilers are key components of today’s embedded processor design platforms for quickly obtaining compiler support and performing early processor architecture exp...