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LCPC
2004
Springer
15 years 7 months ago
Trimaran: An Infrastructure for Research in Instruction-Level Parallelism
Trimaran is an integrated compilation and performance monitoring infrastructure. The architecture space that Trimaran covers is characterized by HPL-PD, a parameterized processor a...
Lakshmi N. Chakrapani, John C. Gyllenhaal, Wen-mei...
HPCA
2009
IEEE
16 years 2 months ago
Prediction router: Yet another low latency on-chip router architecture
Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce th...
Hiroki Matsutani, Michihiro Koibuchi, Hideharu Ama...
ANCS
2008
ACM
15 years 3 months ago
Low power architecture for high speed packet classification
Today's routers need to perform packet classification at wire speed in order to provide critical services such as traffic billing, priority routing and blocking unwanted Inte...
Alan Kennedy, Xiaojun Wang, Zhen Liu, Bin Liu
GCC
2006
Springer
15 years 5 months ago
General Running Service: An Execution Framework for Executing Legacy Program on Grid
Legacy program execution system, which is necessary for Grid to enable users to reuse all legacy programs without reengineering source codes, is still an open problem. We propose ...
Likun Liu, Yongwei Wu, Guangwen Yang, Ruyue Ma, Fe...
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IDMS
1997
Springer
188views Multimedia» more  IDMS 1997»
15 years 5 months ago
An Approach for an Adaptive Visualization in a Mobile Environment
With the evolving availability of wireless communication servicesand of affordable mobile devices such as notebooks or Personal Digital Assistants, mobile computing is becoming wid...
Luc Neumann, Alberto Barbosa Raposo