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    VLSID
    1997
    IEEE
    106views VLSI» more  VLSID 1997»
    Low-Power Configurable Processor Array for DLMS Adaptive Filtering
    15 years 10 months ago
    Low-Power Configurable Processor Array for DLMS Adaptive Filtering
    Download  eprints.iisc.ernet.in
    I n this paper, we first present a pipelined delayed least mean square (DLMS) adaptive filter architecture whose power dissipation meets a specified budget. This low-power archite...
    S. Ramanathan, V. Visvanathan
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    ASAP
    2006
    IEEE
    119views Hardware» more  ASAP 2006»
    From Bit Level Systolic Arrays to HDTV Processor Chips
    15 years 7 months ago
    From Bit Level Systolic Arrays to HDTV Processor Chips
    Download  vada.skku.ac.kr
    The paper starts presents the work initially carried out by Queen's University and RSRE (now Qinetiq) in the development of advanced architectures and microchips based on sys...
    John V. McCanny, Roger F. Woods, John G. McWhirter
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    DAC
    2001
    ACM
    151views Computer Architecture» more  DAC 2001»
    On-Chip Communication Architecture for OC-768 Network Processors
    16 years 6 months ago
    On-Chip Communication Architecture for OC-768 Network Processors
    Download  www.ra.informatik.uni-stuttgart.de
    Faraydon Karim, Anh Nguyen, Sujit Dey, Ramesh R. R...
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    DAC
    2005
    ACM
    102views Computer Architecture» more  DAC 2005»
    Floorplan-aware automated synthesis of bus-based communication architectures
    16 years 6 months ago
    Floorplan-aware automated synthesis of bus-based communication architectures
    Download  www.ics.uci.edu
    Sudeep Pasricha, Nikil D. Dutt, Elaheh Bozorgzadeh...
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    HPCA
    2001
    IEEE
    113views Distributed And Parallel Com...» more  HPCA 2001»
    Quantifying the Impact of Architectural Scaling on Communication
    16 years 6 months ago
    Quantifying the Impact of Architectural Scaling on Communication
    Download  www.cs.rutgers.edu
    Taliver Heath, Samian Kaur, Richard P. Martin, Thu...
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