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HPCA
2008
IEEE
16 years 3 months ago
An OS-based alternative to full hardware coherence on tiled CMPs
The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (CMPs) are expected to become a bottleneck that prevents these architectures from scaling...
Christian Fensch, Marcelo Cintra
130
Voted
CHI
2004
ACM
16 years 3 months ago
Feeling bumps and holes without a haptic interface: the perception of pseudo-haptic textures
We present a new interaction technique to simulate textures in desktop applications without a haptic interface. The proposed technique consists in modifying the motion of the curs...
Anatole Lécuyer, Jean-Marie Burkhardt, Laur...
CLUSTER
2009
IEEE
15 years 10 months ago
Granules: A lightweight, streaming runtime for cloud computing with support, for Map-Reduce
— Cloud computing has gained significant traction in recent years. The Map-Reduce framework is currently the most dominant programming model in cloud computing settings. In this ...
Shrideep Pallickara, Jaliya Ekanayake, Geoffrey Fo...
HPDC
2009
IEEE
15 years 10 months ago
Pluggable parallelisation
This paper presents the concept of pluggable parallelisation that allows scientists to develop “sequential like” codes that can take advantage of multi-core, cluster and grid ...
Rui C. Gonçalves, João Luís S...
114
Voted
IPPS
2007
IEEE
15 years 9 months ago
Pipelining Tradeoffs of Massively Parallel SuperCISC Hardware Functions
Parallel processing using multiple processors is a well-established technique to accelerate many different classes of applications. However, as the density of chips increases, ano...
Colin J. Ihrig, Justin Stander, Alex K. Jones