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99
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DAC
2004
ACM
15 years 3 months ago
Area-efficient instruction set synthesis for reconfigurable system-on-chip designs
Silicon compilers are often used in conjunction with Field Programmable Gate Arrays (FPGAs) to deliver flexibility, fast prototyping, and accelerated time-to-market. Many of these...
Philip Brisk, Adam Kaplan, Majid Sarrafzadeh
91
Voted
ASPDAC
2009
ACM
133views Hardware» more  ASPDAC 2009»
14 years 11 months ago
A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor
Performance evaluation is a serious challenge in designing or optimizing reconfigurable instruction set processors. The conventional approaches based on synthesis and simulations a...
Farhad Mehdipour, Hamid Noori, Bahman Javadi, Hiro...