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WMPI
2004
ACM
15 years 11 months ago
Evaluating kilo-instruction multiprocessors
The ever increasing gap in processor and memory speeds has a very negative impact on performance. One possible solution to overcome this problem is the Kilo-instruction processor. ...
Marco Galluzzi, Ramón Beivide, Valentin Pue...
IFL
2004
Springer
131views Formal Methods» more  IFL 2004»
15 years 11 months ago
Exploiting Single-Assignment Properties to Optimize Message-Passing Programs by Code Transformations
The message-passing paradigm is now widely accepted and used mainly for inter-process communication in distributed memory parallel systems. However, one of its disadvantages is the...
Alfredo Cristóbal-Salas, Andrey Chernykh, E...
ICPP
2007
IEEE
16 years 14 days ago
RECN-IQ: A Cost-Effective Input-Queued Switch Architecture with Congestion Management
As the number of computing and storage nodes keeps increasing, the interconnection network is becoming a key element of many computing and communication systems, where the overall...
Gaspar Mora, Pedro Javier García, Jose Flic...
ISCA
2005
IEEE
181views Hardware» more  ISCA 2005»
15 years 11 months ago
Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors
With the ability to place large numbers of transistors on a single silicon chip, manufacturers have begun developing chip multiprocessors (CMPs) containing multiple processor core...
Evan Speight, Hazim Shafi, Lixin Zhang, Ramakrishn...
HPCA
2009
IEEE
16 years 6 months ago
PageNUCA: Selected policies for page-grain locality management in large shared chip-multiprocessor caches
As the last-level on-chip caches in chip-multiprocessors increase in size, the physical locality of on-chip data becomes important for delivering high performance. The non-uniform...
Mainak Chaudhuri