Sciweavers

56 search results - page 8 / 12
» Asynchronous Design Using Commercial HDL Synthesis Tools
Sort
View
VLSID
1997
IEEE
98views VLSI» more  VLSID 1997»
15 years 1 months ago
Synthesis for Logical Initializability of Synchronous Finite State Machines
—Logical initializability is the property of a gate-level circuit whereby it can be driven to a unique start state when simulated by a three-valued (0, 1, ) simulator. In practic...
Montek Singh, Steven M. Nowick
DATE
2009
IEEE
155views Hardware» more  DATE 2009»
15 years 1 months ago
Automatically mapping applications to a self-reconfiguring platform
The inherent reconfigurability of SRAM-based FPGAs enables the use of configurations optimized for the problem at hand. Optimized configurations are smaller and faster than their g...
Karel Bruneel, Fatma Abouelella, Dirk Stroobandt
ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
15 years 1 months ago
Safe Delay Optimization for Physical Synthesis
-- Physical synthesis is a relatively young field in Electronic Design Automation. Many published optimizations for physical synthesis end up hurting the final result, often by neg...
Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
88
Voted
PLDI
2011
ACM
14 years 11 days ago
Caisson: a hardware description language for secure information flow
Information flow is an important security property that must be incorporated from the ground up, including at hardware design time, to provide a formal basis for a system’s roo...
Xun Li 0001, Mohit Tiwari, Jason Oberg, Vineeth Ka...
ICCAD
2002
IEEE
94views Hardware» more  ICCAD 2002»
15 years 6 months ago
High-level synthesis of distributed logic-memory architectures
Abstract— With the increasing cost of global communication onchip, high-performance designs for data-intensive applications require architectures that distribute hardware resourc...
Chao Huang, Srivaths Ravi, Anand Raghunathan, Nira...