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ATVA
2006
Springer
133views Hardware» more  ATVA 2006»
15 years 1 months ago
Branching-Time Property Preservation Between Real-Time Systems
In the past decades, many formal frameworks (e.g. timed automata and temporal logics) and techniques (e.g. model checking and theorem proving) have been proposed to model a real-ti...
Jinfeng Huang, Marc Geilen, Jeroen Voeten, Henk Co...
71
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CORR
2010
Springer
120views Education» more  CORR 2010»
14 years 9 months ago
State machine models of timing and circuit design
This paper illustrates a technique for specifying the detailed timing, logical operation, and compositional circuit design of digital circuits in terms of ordinary state machines w...
Victor Yodaiken
CORR
2010
Springer
103views Education» more  CORR 2010»
14 years 9 months ago
Probabilistic regular graphs
Deterministic graph grammars generate regular graphs, that form a structural extension of configuration graphs of pushdown systems. In this paper, we study a probabilistic extensio...
Nathalie Bertrand, Christophe Morvan
ENTCS
2006
120views more  ENTCS 2006»
14 years 9 months ago
Temporal Assertions using AspectJ
We present a runtime verification framework for Java programs. Properties can be specified in Linear-time Temporal Logic (LTL) over AspectJ pointcuts. These properties are checked...
Volker Stolz, Eric Bodden
87
Voted
MJ
2006
144views more  MJ 2006»
14 years 9 months ago
Design metal-dot based QCA circuits using SPICE model
This paper proposes a SPICE model development methodology for quantum-dot cellular automata (QCA) cells and presents a SPICE model for QCA cells. The model is validated by simulat...
Rui Tang, Fengming Zhang, Yong-Bin Kim