Sciweavers

690 search results - page 25 / 138
» Automated Architectural Exploration for Signal Processing Al...
Sort
View
DAC
2004
ACM
16 years 2 months ago
Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining
With deep-sub-micron (DSM) technology, statistical timing analysis becomes increasingly crucial to characterize signal transmission over global interconnect wires. In this paper, ...
Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
KDD
2002
ACM
194views Data Mining» more  KDD 2002»
16 years 2 months ago
Scale Space Exploration For Mining Image Information Content
Images are highly complex multidimensional signals, with rich and complicated information content. For this reason they are difficult to analyze through a unique automated approach...
Mariana Ciucu, Patrick Héas, Mihai Datcu, J...
ISCAS
2006
IEEE
122views Hardware» more  ISCAS 2006»
15 years 8 months ago
256-channel integrated neural interface and spatio-temporal signal processor
Abstract- We present an architecture and VLSI implemen- Various strategies in the analysis of spatio-temporal dynamtation of a distributed neural interface and spatio-temporal ics ...
J. N. Y. Aziz, Roman Genov, B. R. Bardakjian, M. D...
TPHOL
2000
IEEE
15 years 5 months ago
Formal Verification of IA-64 Division Algorithms
The IA-64 architecture defers floating point and integer division to software. To ensure correctness and maximum efficiency, Intel provides a number of recommended algorithms which...
John Harrison
DAC
2006
ACM
16 years 2 months ago
Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration
Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based ...
Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Ruten...