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135
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ISCAS
2002
IEEE
124views Hardware» more  ISCAS 2002»
15 years 8 months ago
Performance optimization of multiple memory architectures for DSP
Multiple memory module architecture offers higher performance by providing potentially doubled memory bandwidth. Two key problems in gaining high performance in this kind of archi...
Qingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha
138
Voted
IPPS
2002
IEEE
15 years 8 months ago
Variable Partitioning and Scheduling of Multiple Memory Architectures for DSP
Multiple memory module architecture enjoys higher memory access bandwidth and thus higher performance. Two key problems in gaining high performance in this kind of architecture ar...
Qingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha
124
Voted
DAC
1996
ACM
15 years 7 months ago
Optimal Clock Skew Scheduling Tolerant to Process Variations
1- A methodology is presented in this paper for determining an optimal set of clock path delays for designing high performance VLSI/ULSI-based clock distribution networks. This met...
José Luis Neves, Eby G. Friedman
112
Voted
SOSYM
2008
87views more  SOSYM 2008»
15 years 3 months ago
Model driven design and aspect weaving
Amodelisasimplifiedrepresentationofanaspect of the world for a specific purpose. In complex systems, many aspects are to be handled, from architectural aspects to dynamic behavior,...
Jean-Marc Jézéquel
109
Voted
DAC
1994
ACM
15 years 7 months ago
Design Methodology Management Using Graph Grammars
In this paper, we present a design methodology management system, which assists designers in selecting a suitable design process and invoking the selected sequence of tools on the...
Reid A. Baldwin, Moon-Jung Chung