Sciweavers

471 search results - page 35 / 95
» Automated Design of Misaligned-Carbon-Nanotube-Immune Circui...
Sort
View
ICCAD
1999
IEEE
80views Hardware» more  ICCAD 1999»
15 years 3 months ago
What is the cost of delay insensitivity?
Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behaviour. Asynchronous spee...
Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, ...
VTS
2005
IEEE
89views Hardware» more  VTS 2005»
15 years 4 months ago
Synthesis of Low Power CED Circuits Based on Parity Codes
An automated design procedure is described for synthesizing circuits with low power concurrent error detection. It is based on pre-synthesis selection of a parity-check code follo...
Shalini Ghosh, Sugato Basu, Nur A. Touba
GLVLSI
2007
IEEE
171views VLSI» more  GLVLSI 2007»
15 years 5 months ago
Combinational equivalence checking for threshold logic circuits
Threshold logic is gaining prominence as an alternative to Boolean logic. The main reason for this trend is the availability of devices that implement these circuits efficiently (...
Tejaswi Gowda, Sarma B. K. Vrudhula, Goran Konjevo...
DAC
2010
ACM
15 years 2 months ago
Post-silicon validation opportunities, challenges and recent advances
Post-silicon validation is used to detect and fix bugs in integrated circuits and systems after manufacture. Due to sheer design complexity, it is nearly impossible to detect and ...
Subhasish Mitra, Sanjit A. Seshia, Nicola Nicolici
DAC
2003
ACM
16 years 3 days ago
A TBR-based trajectory piecewise-linear algorithm for generating accurate low-order models for nonlinear analog circuits and MEM
In this paper we propose a method for generating reduced models for a class of nonlinear dynamical systems, based on truncated balanced realization (TBR) algorithm and a recently ...
Dmitry Vasilyev, Michal Rewienski, Jacob White