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127
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SPAA
2006
ACM
15 years 8 months ago
Modeling instruction placement on a spatial architecture
In response to current technology scaling trends, architects are developing a new style of processor, known as spatial computers. A spatial computer is composed of hundreds or eve...
Martha Mercaldi, Steven Swanson, Andrew Petersen, ...
ISSS
2002
IEEE
142views Hardware» more  ISSS 2002»
15 years 7 months ago
Round-Robin Arbiter Design and Generation
In this paper, we introduce a Round–robin Arbiter Generator (RAG) tool. The RAG tool can generate a design for a Bus Arbiter (BA). The BA is able to handle the exact number of b...
Vincent John Mooney III, George F. Riley, Eung S. ...
146
Voted
IPPS
2006
IEEE
15 years 8 months ago
FPGA implementation of a license plate recognition SoC using automatically generated streaming accelerators
Modern FPGA platforms provide the hardware and software infrastructure for building a bus-based System on Chip (SoC) that meet the applications requirements. The designer can cust...
Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan L...
88
Voted
IPPS
2007
IEEE
15 years 8 months ago
Cost-Driven Hybrid Configuration Prefetching for Partial Reconfigurable Coprocessor
Reconfigurable computing systems have developed the capability of changing the configuration of the reconfigurable coprocessor multiple times during the course of a program. Howev...
Ying Chen, Simon Y. Chen
138
Voted
ARCS
2008
Springer
15 years 4 months ago
An Optimized ZGEMM Implementation for the Cell BE
: The architecture of the IBM Cell BE processor represents a new approach for designing CPUs. The fast execution of legacy software has to stand back in order to achieve very high ...
Timo Schneider, Torsten Hoefler, Simon Wunderlich,...