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DFT
2006
IEEE
203views VLSI» more  DFT 2006»
15 years 3 months ago
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
Ondrej Novák, Zdenek Plíva, Jiri Jen...
ENTCS
2002
144views more  ENTCS 2002»
14 years 9 months ago
Logics and Multi-agents: towards a new symbolic model of cognition
Abstract The last edition of CLIMA, held in 2001 in Paphos (Cyprus) ended with a panel session on the role of Computational Logic (CL) in Multi-Agent Systems (MAS). Two dimensions ...
Paolo Torroni

Publication
351views
16 years 10 months ago
Synthesizable High Level Hardware Descriptions
Modern hardware description languages support code-generation constructs like generate/endgenerate in Verilog. These constructs are intended to describe regular or parameterized ha...
Jennifer Gillenwater, Gregory Malecha, Cherif Sala...
ICCS
2001
Springer
15 years 2 months ago
Optimizing Sparse Matrix Computations for Register Reuse in SPARSITY
Abstract. Sparse matrix-vector multiplication is an important computational kernel that tends to perform poorly on modern processors, largely because of its high ratio of memory op...
Eun-Jin Im, Katherine A. Yelick
PAAPP
2002
76views more  PAAPP 2002»
14 years 9 months ago
Performance of PDE solvers on a self-optimizing NUMA architecture
Abstract. The performance of shared-memory (OpenMP) implementations of three different PDE solver kernels representing finite difference methods, finite volume methods, and spectra...
Sverker Holmgren, Markus Nordén, Jarmo Rant...