41 search results - page 7 / 9 » Automatic Generation of Synchronous Test Patterns for Asynch... |
63
Voted
ATS
2009
IEEE
15 years 5 months ago
2009
IEEE
SAT-based automatic test pattern generation has several advantages compared to conventional structural procedures, yet often yields too large test sets. We present a dynamic compa...
112
Voted
DFT
2006
IEEE
15 years 4 months ago
2006
IEEE
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
107
Voted
INTEGRATION
2006
14 years 10 months ago
2006
Improving testability during the early stages of high-level synthesis has several benefits including reduced test hardware overheads, reduced test costs, reduced design iterations...
IOLTS
2008
IEEE
15 years 4 months ago
2008
IEEE
Present and future semiconductor technologies are characterized by increasing parameters variations as well as an increasing susceptibility to external disturbances. Transient err...
91
Voted
DT
2000
14 years 10 months ago
2000
Effective high-level ATPG tools are increasingly needed, as an essential element in the quest for reducing as much as possible the designer work on gate-level descriptions. We pro...