Hardware description languages (HDLs) are used today to describe circuits at all levels. In large HDL programs, there is a need for source code reduction techniques to address a my...
Edmund M. Clarke, Masahiro Fujita, Sreeranga P. Ra...
Abstract: We present a novel approach to the verification of functional-logic programs. For our verification purposes, equational reasoning is not valid due to the presence of non-...
This poster paper investigates the potential of single and multiobjective genetic operators with an object-oriented conceptual design space. Using cohesion as an objective fitness...
For use in earlier approaches to automated module interface adaptation, we seek a restricted form of program synthesis. Given some typing assumptions and a desired result type, we ...
— We present techniques for analyzing the source code of distributed Java applications, and building finite models of their behaviour. The models are labelled transition systems...