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DAC
1996
ACM
15 years 1 months ago
Pseudorandom-Pattern Test Resistance in High-Performance DSP Datapaths
The testability of basic DSP datapath structures using pseudorandom built-in self-test techniques is examined. The addition of variance mismatched signals is identified as a testi...
Laurence Goodby, Alex Orailoglu
IOLTS
2000
IEEE
105views Hardware» more  IOLTS 2000»
15 years 1 months ago
Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults
The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. A...
Patrick Girard, Christian Landrault, Serge Pravoss...
ITC
1997
IEEE
129views Hardware» more  ITC 1997»
15 years 1 months ago
On Using Machine Learning for Logic BIST
This paper presents a new approach for designing test sequences to be generated on–chip. The proposed technique is based on machine learning, and provides a way to generate effi...
Christophe Fagot, Patrick Girard, Christian Landra...
VLSID
2009
IEEE
150views VLSI» more  VLSID 2009»
15 years 10 months ago
TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis
We present the automatic test pattern generator TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully ...
Alejandro Czutro, Ilia Polian, Matthew D. T. Lewis...
ICCD
2004
IEEE
134views Hardware» more  ICCD 2004»
15 years 6 months ago
An Automatic Test Pattern Generation Framework for Combinational Threshold Logic Networks
— We propose an automatic test pattern generation (ATPG) framework for combinational threshold networks. The motivation behind this work lies in the fact that many emerging nanot...
Pallav Gupta, Rui Zhang, Niraj K. Jha