47 search results - page 4 / 10 » Automatic memory reductions for RTL model verification |
101
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VLSID
2001
IEEE
16 years 1 days ago
2001
IEEE
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
105
Voted
EMSOFT
2006
Springer
15 years 3 months ago
2006
Springer
Upper bounds on worst-case execution times, which are commonly called WCET, are a prerequisite for validating the temporal correctness of tasks in a real-time system. Due to the e...
110
Voted
FORMATS
2007
Springer
15 years 3 months ago
2007
Springer
Abstract. We describe a partial order reduction technique for a realtime component model. Components are described as timed automata with data ports, which can be composed in stati...
CODES
2009
IEEE
15 years 3 months ago
2009
IEEE
In this paper, we propose an effective automatic generation approach for a Cycle-Count Accurate Memory Model (CCAMM) from the Clocked Finite State Machine (CFSM) of the Cycle Accu...
90
Voted
CAV
2004
Springer
15 years 3 months ago
2004
Springer
Sequential consistency is the archetypal correctness condition for the memory protocols of shared-memory multiprocessors. Typically, such protocols are parameterized by the number ...