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» Automatic memory reductions for RTL model verification
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ENTCS
2006
109views more  ENTCS 2006»
14 years 10 months ago
Incremental Verification for On-the-Fly Controller Synthesis
The CIRCA system automatically synthesizes hard real-time discrete event controllers from plant and environment descriptions. CIRCA's automatically-synthesized controllers pr...
David J. Musliner, Michael J. S. Pelican, Robert P...
FAC
2008
100views more  FAC 2008»
14 years 10 months ago
Slicing communicating automata specifications: polynomial algorithms for model reduction
Abstract. Slicing is a program analysis technique that was originally introduced to improve program debugging and understanding. The purpose of a slicing algorithm is to remove the...
Sébastien Labbé, Jean-Pierre Gallois
IPPS
2007
IEEE
15 years 4 months ago
A global address space framework for locality aware scheduling of block-sparse computations
In this paper, we present a mechanism for automatic management of the memory hierarchy, including secondary storage, in the context of a global address space parallel programming ...
Sriram Krishnamoorthy, Ümit V. Çataly&...
CSFW
2009
IEEE
15 years 1 months ago
Using ProVerif to Analyze Protocols with Diffie-Hellman Exponentiation
ProVerif is one of the most successful tools for cryptographic protocol analysis. However, dealing with algebraic properties of operators such as the exclusive OR (XOR) and Diffie-...
Ralf Küsters, Tomasz Truderung
DATE
2008
IEEE
168views Hardware» more  DATE 2008»
15 years 4 months ago
Cycle-approximate Retargetable Performance Estimation at the Transaction Level
This paper presents a novel cycle-approximate performance estimation technique for automatically generated transaction level models (TLMs) for heterogeneous multicore designs. The...
Yonghyun Hwang, Samar Abdi, Daniel Gajski