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ATS
2010
IEEE
239views Hardware» more  ATS 2010»
14 years 5 months ago
Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level
In recent technology nodes, reliability is considered a part of the standard design flow at all levels of embedded system design. While techniques that use only low-level models at...
Michael A. Kochte, Christian G. Zoellin, Rafal Bar...
RTCSA
1999
IEEE
15 years 2 months ago
Pipeline Timing Analysis Using a Trace-Driven Simulator
In this paper we present a technique for Worst-Case Execution Time WCET analysis for pipelined processors. Our technique uses a standard simulator instead of special-purpose pipel...
Jakob Engblom, Andreas Ermedahl
AAAI
1994
14 years 11 months ago
Parsing Embedded Clauses with Distributed Neural Networks
A distributed neural network model called SPEC for processing sentences with recursive relative clauses is described. The model is based on separating the tasks of segmenting the ...
Risto Miikkulainen, Dennis Bijwaard
CASES
2001
ACM
15 years 1 months ago
Storage allocation for embedded processors
In an embedded system, it is common to have several memory areas with different properties, such as access time and size. An access to a specific memory area is usually restricted...
Jan Sjödin, Carl von Platen
FDL
2006
IEEE
15 years 4 months ago
Reusing Real-Time Systems Design Experience
To ensure correctness and performance of real-time embedded systems, early evaluation of properties is needed. Based on design experience for real-time systems and using the conce...
Oana Florescu, Jeroen Voeten, Marcel Verhoef, Henk...