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» Bayesian Algorithmic Mechanism Design
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DFT
2006
IEEE
203views VLSI» more  DFT 2006»
15 years 6 months ago
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
Ondrej Novák, Zdenek Plíva, Jiri Jen...
BMCBI
2010
167views more  BMCBI 2010»
15 years 20 days ago
Inference of sparse combinatorial-control networks from gene-expression data: a message passing approach
Background: Transcriptional gene regulation is one of the most important mechanisms in controlling many essential cellular processes, including cell development, cell-cycle contro...
Marc Bailly-Bechet, Alfredo Braunstein, Andrea Pag...
107
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CACM
2008
84views more  CACM 2008»
15 years 20 days ago
The emergence of a networking primitive in wireless sensor networks
The wireless sensor network community approached netabstractions as an open question, allowing answers to emerge with time and experience. The Trickle algorithm has become a basic...
Philip Levis, Eric A. Brewer, David E. Culler, Dav...
102
Voted
DAC
2006
ACM
16 years 1 months ago
Prediction-based flow control for network-on-chip traffic
Networks-on-Chip (NoC) architectures provide a scalable solution to on-chip communication problem but the bandwidth offered by NoCs can be utilized efficiently only in presence of...
Ümit Y. Ogras, Radu Marculescu
85
Voted
IWMM
2007
Springer
110views Hardware» more  IWMM 2007»
15 years 6 months ago
Path: page access tracking to improve memory management
Traditionally, operating systems use a coarse approximation of memory accesses to implement memory management algorithms by monitoring page faults or scanning page table entries. ...
Reza Azimi, Livio Soares, Michael Stumm, Thomas Wa...