317 search results - page 53 / 64 » Benchmarking weak memory models |
115
click to vote
MICRO
2010
IEEE
14 years 10 months ago
2010
IEEE
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
LCTRTS
2004
Springer
15 years 5 months ago
2004
Springer
This paper presents Spinach, a new simulator toolset specifically designed to target programmable network interface architectures. Spinach models both system components that are ...
104
click to vote
PLDI
2011
ACM
14 years 2 months ago
2011
ACM
The most intuitive memory consistency model for shared-memory multi-threaded programming is sequential consistency (SC). However, current concurrent programming languages support ...
124
click to vote
ISCA
2012
IEEE
13 years 2 months ago
2012
IEEE
Data-race freedom is a valuable safety property for multithreaded programs that helps with catching bugs, simplifying memory consistency model semantics, and verifying and enforci...
WWW
2009
ACM
16 years 11 days ago
2009
ACM
The performance of server-side applications is becoming increasingly important as more applications exploit the Web application model. Extensive work has been done to improve the ...