Sciweavers

613 search results - page 17 / 123
» Block cache for embedded systems
Sort
View
ISVLSI
2003
IEEE
101views VLSI» more  ISVLSI 2003»
15 years 5 months ago
Energy Benefits of a Configurable Line Size Cache for Embedded Systems
Previous work has shown that cache line sizes impact performance differently for different desktop programs – some programs work better with small line sizes, others with larger...
Chuanjun Zhang, Frank Vahid, Walid A. Najjar
ICCD
2006
IEEE
121views Hardware» more  ICCD 2006»
15 years 8 months ago
A Low Power Highly Associative Cache for Embedded Systems
—Reducing energy consumption is an important issue for battery powered embedded computing systems. Content Addressable Memory (CAM)-based Highly-Associative Caches (HAC) are wide...
Chuanjun Zhang
ICCAD
1999
IEEE
92views Hardware» more  ICCAD 1999»
15 years 4 months ago
Interface and cache power exploration for core-based embedded system design
Minimizing power consumption is of paramount importance during the design of embedded (mobile computing) systems that come as systems-ona-chip, since interdependencies of design c...
Tony Givargis, Jörg Henkel, Frank Vahid
VLDB
2001
ACM
104views Database» more  VLDB 2001»
15 years 4 months ago
Cache Fusion: Extending Shared-Disk Clusters with Shared Caches
Cache Fusion TM is a fundamental component of Oracle’s Real Application Cluster configuration, a shared-cache clustered-database architecture that transparently extends databas...
Tirthankar Lahiri, Vinay Srihari, Wilson Chan, N. ...
CASES
2007
ACM
15 years 3 months ago
Fragment cache management for dynamic binary translators in embedded systems with scratchpad
Dynamic binary translation (DBT) has been used to achieve numerous goals (e.g., better performance) for general-purpose computers. Recently, DBT has also attracted attention for e...
José Baiocchi, Bruce R. Childers, Jack W. D...