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87
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ISCA
2007
IEEE
143views Hardware» more  ISCA 2007»
15 years 6 months ago
Interconnect design considerations for large NUCA caches
The ever increasing sizes of on-chip caches and the growing domination of wire delay necessitate significant changes to cache hierarchy design methodologies. Many recent proposal...
Naveen Muralimanohar, Rajeev Balasubramonian
99
Voted
HPCC
2009
Springer
15 years 5 months ago
Grid Network Dimensioning by Modeling the Deadline Constrained Bulk Data Transfers
—Grid applications need to move large amounts of data between distributed resources within deterministic time frames. In most cases it is possible to specify the volume and the d...
Kashif Munir, Pascale Vicat-Blanc Primet, Michael ...
116
Voted
IPPS
1999
IEEE
15 years 4 months ago
Cascaded Execution: Speeding Up Unparallelized Execution on Shared-Memory Multiprocessors
Both inherently sequential code and limitations of analysis techniques prevent full parallelization of many applications by parallelizing compilers. Amdahl's Law tells us tha...
Ruth E. Anderson, Thu D. Nguyen, John Zahorjan
137
Voted
MICRO
1999
IEEE
143views Hardware» more  MICRO 1999»
15 years 4 months ago
Code Transformations to Improve Memory Parallelism
Current microprocessors incorporate techniques to exploit instruction-level parallelism (ILP). However, previous work has shown that these ILP techniques are less effective in rem...
Vijay S. Pai, Sarita V. Adve
122
Voted
CHES
2006
Springer
158views Cryptology» more  CHES 2006»
15 years 4 months ago
Hardware/Software Co-design of Elliptic Curve Cryptography on an 8051 Microcontroller
8-bit microcontrollers like the 8051 still hold a considerable share of the embedded systems market and dominate in the smart card industry. The performance of 8-bit microcontrolle...
Manuel Koschuch, Joachim Lechner, Andreas Weitzer,...