Efficient system-level design is increasingly relying on hierarchical design-space exploration, as well as compositional methods, to shorten time-to-market, leverage design re-use...
Tools have been developed that enable in-circuit testing of content processing hardware. The tools automate test and verification of new circuits using data from a predefined te...
ESIM is a simulation tool that integrates logic fault and design error simulation for logic circuits. It targets several design error and fault models, and uses a novel mix of sim...
: Electromigration induced degradation in integrated circuits has been accelerated by continuous scaling of device dimensions. We present a methodology for synthesizing high-reliab...
Traditional corner analysis fails to guarantee a target yield for a given performance metric. However, recently proposed solutions, in the form of statistical timing analysis, whi...