83 search results - page 11 / 17 » Bounding Loop Iterations for Timing Analysis |
ASPDAC
2010
ACM
14 years 9 months ago
2010
ACM
Level-sensitive transparent latches are widely used in high-performance sequential circuit designs. Under process variations, the timing of a transparently latched circuit will ada...
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JISE
1998
14 years 11 months ago
1998
In the framework of perfect loop nests with uniform dependences, tiling has been extensively studied as a source-to-source program transformation. We build upon recent results by ...
EUROPAR
2004
Springer
15 years 5 months ago
2004
Springer
Several optimization techniques are hindered by uncertainties about the control flow in a program, which can generally not be determined by static methods at compile time. We pres...
VLSID
1999
IEEE
15 years 4 months ago
1999
IEEE
We describe an improved iterationless approach for computing the effective capacitance of an interconnect load at a driving gate output. The speed and accuracy of our approach mak...
IPPS
2007
IEEE
15 years 6 months ago
2007
IEEE
Compositional performance analysis iteratively alternates local scheduling analysis techniques and output event model propagation between system components to enable performance a...