30 search results - page 5 / 6 » Buffer Insertion with Accurate Gate and Interconnect Delay C... |
DAC
1996
ACM
15 years 1 months ago
1996
ACM
To reduce the number of synthesis and layout iterations, we present a new delay optimization technique, which inserts buers based on back-annotated detailed routing information. D...
TVLSI
2002
14 years 9 months ago
2002
Abstract--This paper provides a high level survey of the increasing effects of on-chip inductance. These effects are classified into desirable and nondesirable effects. Among the u...
ISQED
2002
IEEE
15 years 2 months ago
2002
IEEE
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance. Buffer insertion/sizing and wire sizing are ...
VLSID
2002
IEEE
15 years 10 months ago
2002
IEEE
Interconnect delay has become a critical factor in determining the performance of integrated circuits. Routing and buffering are powerful means of improving the circuit speed and ...
VLSID
1999
IEEE
15 years 1 months ago
1999
IEEE
We describe an improved iterationless approach for computing the effective capacitance of an interconnect load at a driving gate output. The speed and accuracy of our approach mak...