40 search results - page 6 / 8 » Buffering Interconnect for Multicore Processor Designs |
ISPASS
2007
IEEE
14 years 15 days ago
2007
IEEE
Parameter variation due to manufacturing error will be an unavoidable consequence of technology scaling in future generations. The impact of random variation in physical factors s...
HPDC
2009
IEEE
14 years 29 days ago
2009
IEEE
Since the advent of electronic computing, the processors’ clock speed has risen tremendously. Now that energy efficiency requirements have stopped that trend, the number of proc...
CODES
2007
IEEE
14 years 17 days ago
2007
IEEE
Performance analysis of microprocessors is a critical step in defining the microarchitecture, prior to register-transfer-level (RTL) design. In complex chip multiprocessor systems...
EUROPAR
2009
Springer
13 years 10 months ago
2009
Springer
The Cell Broadband Engine (Cell BE) is a heterogeneous multi-core processor specifically designed to exploit thread-level parallelism. Its memory model comprehends a common shared ...
PPOPP
2006
ACM
14 years 5 days ago
2006
ACM
Applications need to become more concurrent to take advantage of the increased computational power provided by chip level multiprocessing. Programmers have traditionally managed t...