56 search results - page 3 / 12 » Buffering global interconnects in structured ASIC design |
DAC
2005
ACM
15 years 10 months ago
2005
ACM
ASIC provides more than an order of magnitude advantage in terms of density, speed, and power requirement per gate. However, economic (cost of masks) and technological (deep micro...
SLIP
2009
ACM
15 years 4 months ago
2009
ACM
Different interconnection structures have been proposed to solve the performance limitation caused by scaling of on-chip global wires. In this paper, we give an overview of curre...
90
Voted
ISCAS
2005
IEEE
15 years 3 months ago
2005
IEEE
— Interconnect delays are increasingly becoming the dominant source of performance degradation in the nano-meter regime, largely because of disturbances that result from parasiti...
ICCAD
1996
IEEE
15 years 1 months ago
1996
IEEE
Abstract -- Current day behavioral-synthesis techniques produce architectures that are power-inefficient in the interconnect. Experiments have demonstrated that in synthesized desi...
ASPDAC
2008
ACM
14 years 11 months ago
2008
ACM
Accurate modeling of delay, power, and area of interconnections early in the design phase is crucial for effective system-level optimization. Models presently used in system-level...