74 search results - page 6 / 15 » Built-in test generation for synchronous sequential circuits |
ET
2000
14 years 9 months ago
2000
The paper presents a novel hierarchical approach to test pattern generation for sequential circuits based on an input model of mixed-level decision diagrams. A method that handles,...
VLSID
1997
IEEE
15 years 1 months ago
1997
IEEE
The problem of test generation belongs to the class of NP-complete problems and it is becoming more and more di cult as the complexity of VLSI circuits increases, and as long as e...
DATE
1997
IEEE
15 years 1 months ago
1997
IEEE
A new method for state justi cation is proposed for sequential circuit test generation. The linear list of states dynamically obtained during the derivation of test vectors is use...
DATE
2003
IEEE
15 years 2 months ago
2003
IEEE
VLSID
1995
IEEE
15 years 29 days ago
1995
IEEE