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DATE
2006
IEEE
134views Hardware» more  DATE 2006»
15 years 10 months ago
ASIP-based multiprocessor SoC design for simple and double binary turbo decoding
This paper presents a new multiprocessor platform for high throughput turbo decoding. The proposed platform is based on a new configurable ASIP combined with an efficient memory a...
Olivier Muller, Amer Baghdadi, Michel Jéz&e...
DATE
2006
IEEE
91views Hardware» more  DATE 2006»
15 years 10 months ago
Dynamic partitioning of processing and memory resources in embedded MPSoC architectures
Liping Xue, Ozcan Ozturk, Feihui Li, Mahmut T. Kan...
DFT
2006
IEEE
105views VLSI» more  DFT 2006»
15 years 10 months ago
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving
1 High temperature has become a major problem for system-on-chip testing. In order to reduce the test time while keeping the temperature of the chip under test within a safe range,...
Zhiyuan He, Zebo Peng, Petru Eles, Paul M. Rosinge...
DFT
2006
IEEE
143views VLSI» more  DFT 2006»
15 years 10 months ago
Defect Tolerant and Energy Economized DSP Plane of a 3-D Heterogeneous SoC
This paper1 discusses a defect tolerant and energy economized computing array for the DSP plane of a 3-D Heterogeneous System on a Chip. We present the J-platform, which employs c...
Vijay K. Jain, Glenn H. Chapman