267 search results - page 11 / 54 » CHIPS: Custom Hardware Instruction Processor Synthesis |
HPCA
2011
IEEE
14 years 1 months ago
2011
IEEE
Queues are commonly used in multithreaded programs for synchronization and communication. However, because software queues tend to be too expensive to support finegrained paralle...
ASPDAC
2009
ACM
14 years 10 months ago
2009
ACM
Performance evaluation is a serious challenge in designing or optimizing reconfigurable instruction set processors. The conventional approaches based on synthesis and simulations a...
ICCD
2004
IEEE
15 years 6 months ago
2004
IEEE
Network-on-chip (NoC) has been proposed as a solution for the communication challenges of System-on-chip (SoC) design in the nanoscale regime. SoC design offers the opportunity fo...
FPL
2005
Springer
15 years 3 months ago
2005
Springer
Abstract. We propose CUSTARD — CUStomisable Threaded ARchitecture — a soft processor design space that combines support for multiple hardware threads and automatically generate...
CASES
2000
ACM
15 years 1 months ago
2000
ACM
This paper introduces the notion of a Flexible Instruction Processor (FIP) for systematic customisation of instruction processor design and implementation. The features of our app...