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» CHIPS: Custom Hardware Instruction Processor Synthesis
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VLSID
2005
IEEE
102views VLSI» more  VLSID 2005»
15 years 10 months ago
Integrated On-Chip Storage Evaluation in ASIP Synthesis
An Application Specific Instruction Set Processor (ASIP) exploits special characteristics of the given application(s) to meet the desired performance, cost and power requirements....
Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
FCCM
2006
IEEE
125views VLSI» more  FCCM 2006»
15 years 3 months ago
A Multithreaded Soft Processor for SoPC Area Reduction
The growth in size and performance of Field Programmable Gate Arrays (FPGAs) has compelled System-on-aProgrammable-Chip (SoPC) designers to use soft processors for controlling sys...
Blair Fort, Davor Capalija, Zvonko G. Vranesic, St...
CAL
2006
14 years 9 months ago
A case for fault tolerance and performance enhancement using chip multi-processors
This paper makes a case for using multi-core processors to simultaneously achieve transient-fault tolerance and performance enhancement. Our approach is extended from a recent late...
Huiyang Zhou
FPL
2007
Springer
99views Hardware» more  FPL 2007»
15 years 1 months ago
Disjoint Pattern Enumeration for Custom Instructions Identification
Extensible processors allow addition of application-specific custom instructions to the core instruction set architecture. These custom instructions are selected through an analys...
Pan Yu, Tulika Mitra
FCCM
2003
IEEE
123views VLSI» more  FCCM 2003»
15 years 3 months ago
FPGA-based SIMD Processor
A massively parallel single instruction multiple data stream (SIMD) processor designed specifically for cryptographic key search applications is presented. This design aims to ex...
Stanley Y. C. Li, Gap C. K. Cheuk, Kin-Hong Lee, P...