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» CMP design space exploration subject to physical constraints
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IEEEPACT
2008
IEEE
15 years 4 months ago
Distributed cooperative caching
This paper presents the Distributed Cooperative Caching, a scalable and energy-efficient scheme to manage chip multiprocessor (CMP) cache resources. The proposed configuration is...
Enric Herrero, José González, Ramon ...
TEI
2010
ACM
129views Hardware» more  TEI 2010»
14 years 9 months ago
Silent mutations: physical-digital interactions in spaces
Many installations research efforts today explore how to engage participants with embedded digital content and applications in interactive environments. Yet the interactive design...
Claudia Rébola Winegarden, Nicholas Komor, ...
CODES
2003
IEEE
15 years 2 months ago
Design space minimization with timing and code size optimization for embedded DSP
One of the most challenging problems in high-level synthesis is how to quickly explore a wide range of design options to achieve high-quality designs. This paper presents an Integ...
Qingfeng Zhuge, Zili Shao, Bin Xiao, Edwin Hsing-M...
GLVLSI
2006
IEEE
101views VLSI» more  GLVLSI 2006»
15 years 3 months ago
Measurement and characterization of pattern dependent process variations of interconnect resistance, capacitance and inductance
Process variations have become a serious concern for nanometer technologies. The interconnect and device variations include interand intra-die variations of geometries, as well as...
Xiaoning Qi, Alex Gyure, Yansheng Luo, Sam C. Lo, ...
EUC
2006
Springer
15 years 1 months ago
Co-optimization of Performance and Power in a Superscalar Processor Design
Abstract. As process technology scales down, power wall starts to hinder improvements in processor performance. Performance optimization has to proceed under a power constraint. Th...
Yongxin Zhu, Weng-Fai Wong, Stefan Andrei