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CGO
2004
IEEE
15 years 1 months ago
Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors
Pre-execution techniques have received much attention as an effective way of prefetching cache blocks to tolerate the everincreasing memory latency. A number of pre-execution tech...
Dongkeun Kim, Shih-Wei Liao, Perry H. Wang, Juan d...
CODES
2004
IEEE
15 years 1 months ago
Power analysis of system-level on-chip communication architectures
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
Kanishka Lahiri, Anand Raghunathan
CODES
2004
IEEE
15 years 1 months ago
Operation tables for scheduling in the presence of incomplete bypassing
Register bypassing is a powerful and widely used feature in modern processors to eliminate certain data hazards. Although complete bypassing is ideal for performance, bypassing ha...
Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, ...
ECOOPWEXCEPTION
2006
Springer
15 years 1 months ago
Exception Handling and Asynchronous Active Objects: Issues and Proposal
Asynchronous Active Objects (AAOs), primarily exemplied by actors [1], nowadays exist in many forms (various kinds of actors, agents and components) and are more and more used beca...
Christophe Dony, Christelle Urtado, Sylvain Vautti...
EDBTW
2006
Springer
15 years 1 months ago
Spatio-temporal Aggregates over Streaming Geospatial Image Data
Geospatial image data obtained by satellites and aircraft are increasingly important to a wide range of applications, such as disaster management, climatology, and environmental m...
Jie Zhang