869 search results - page 24 / 174 » Cache Architectures for Reconfigurable Hardware |
73
Voted
ERSA
2009
14 years 7 months ago
2009
In this paper, we introduce the Woolcano reconfigurable processor architecture. The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary Processing Uni...
ISCA
1990
IEEE
15 years 1 months ago
1990
IEEE
An adaptive cache coherence mechanism exploits semantic information about the expected or observed access behavior of particular data objects. We contend that, in distributed shar...
FCCM
1999
IEEE
15 years 2 months ago
1999
IEEE
Technology scaling of CMOS processes brings relatively faster transistors (gates) and slower interconnects (wires), making viable the addition of reconfigurability to increase per...
IPPS
2007
IEEE
15 years 4 months ago
2007
IEEE
An innovative technique to model and simulate partial and dynamic reconfigurable processors is presented in this paper. The basis for development is a SystemC kernel modified for ...
ARCS
2006
Springer
15 years 1 months ago
2006
Springer
We present a new concept as well as the implementation of a reconfiguration manager for a FPGA-based reconfigurable platform, the Erlangen Slot Machine (ESM). One main advantage of...