869 search results - page 44 / 174 » Cache Architectures for Reconfigurable Hardware |
DSD
2003
IEEE
15 years 3 months ago
2003
IEEE
With shrinking feature size of silicon fabrication technology, architects are putting more and more logic into a single die. While one might opt to use these transistors for build...
IPPS
2006
IEEE
15 years 3 months ago
2006
IEEE
In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained reconfigurable array architect...
105
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IPPS
2006
IEEE
15 years 3 months ago
2006
IEEE
FPGA chips in reconfigurable computer systems are used as malleable coprocessors where components of a hardware library of functions can be configured as needed. As the number of ...
118
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ISCA
2005
IEEE
15 years 3 months ago
2005
IEEE
With the ability to place large numbers of transistors on a single silicon chip, manufacturers have begun developing chip multiprocessors (CMPs) containing multiple processor core...
ARC
2008
Springer
14 years 11 months ago
2008
Springer
Abstract. Loops are an important source of optimization. In this paper, we address such optimizations for those cases when loops contain kernels mapped on reconfigurable fabric. We...