Sciweavers

869 search results - page 66 / 174
» Cache Architectures for Reconfigurable Hardware
Sort
View
IPPS
2007
IEEE
15 years 4 months ago
An Architectural Framework for Automated Streaming Kernel Selection
Hardware accelerators are increasingly used to extend the computational capabilities of baseline scalar processors to meet the growing performance and power requirements of embedd...
Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan L...
FPL
2007
Springer
120views Hardware» more  FPL 2007»
15 years 4 months ago
Design Methodology and Trade-offs Analysis for Parameterized Dynamically Reconfigurable Processor Arrays
In this paper, we propose a Dynamically Reconfigurable Processor Array (DRPA) generator which can generate various types of DRPAs. Our target DRPA architecture is fully parameter...
Yohei Hasegawa, Hideharu Amano
PACS
2000
Springer
121views Hardware» more  PACS 2000»
15 years 1 months ago
Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power
Reducing the supply voltage to reduce dynamic power consumption in CMOS devices, inadvertently will lead to an exponential increase in leakage power dissipation. In this work we ex...
Stefanos Kaxiras, Zhigang Hu, Girija J. Narlikar, ...
MATA
2004
Springer
199views Communications» more  MATA 2004»
15 years 3 months ago
Configuration Management for Networked Reconfigurable Embedded Devices
Distribution of product updates to embedded devices can increase product lifetimes for consumers and boost revenues for vendors. Dynamic provisioning of application solutions to e...
Timothy O'Sullivan, Richard Studdert
DATE
2002
IEEE
84views Hardware» more  DATE 2002»
15 years 2 months ago
Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications
Microprocessors are today getting more and more inefficient for a growing range of applications. Its principles -The Von Neumann paradigm[3]- based on the sequential execution of ...
Gilles Sassatelli, Lionel Torres, Pascal Benoit, T...