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Cache-Oblivious Algorithms and Data Structures
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Maximizing Spare Utilization by Virtually Reorganizing Faulty Cache Lines
14 years 10 months ago
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—Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Since a large fraction of chip area is devoted to on-...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...
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