347 search results - page 17 / 70 » Caching processor general registers |
CC
2008
Springer
14 years 11 months ago
2008
Springer
Heterogeneous multi-core and streaming architectures such as the GPU, Cell, ClearSpeed, and Imagine processors have better power/ performance ratios and memory bandwidth than tradi...
IPPS
2000
IEEE
15 years 2 months ago
2000
IEEE
Time skewing is a compile-time optimization that can provide arbitrarily high cache hit rates for a class of iterative calculations, given a sufficient number of time steps and s...
MICRO
2006
IEEE
15 years 3 months ago
2006
IEEE
We present and evaluate the idea of adaptive processor cache management. Specifically, we describe a novel and general scheme by which we can combine any two cache management alg...
VLSISP
2008
14 years 9 months ago
2008
The compiler is generally regarded as the most important software component that supports a processor design to achieve success. This paper describes our application of the open re...
TCAD
2010
14 years 4 months ago
2010
The last decade has witnessed the emergence of the application-specific instruction-set processor (ASIP) as a viable platform for embedded systems. Extensible ASIPs allow the user ...