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CHES
2007
Springer
327views Cryptology» more  CHES 2007»
15 years 3 months ago
On the Power of Bitslice Implementation on Intel Core2 Processor
Abstract. This paper discusses the state-of-the-art fast software implementation of block ciphers on Intel’s new microprocessor Core2, particularly concentrating on “bitslice i...
Mitsuru Matsui, Junko Nakajima
SIGMETRICS
2003
ACM
199views Hardware» more  SIGMETRICS 2003»
15 years 2 months ago
Data cache locking for higher program predictability
Caches have become increasingly important with the widening gap between main memory and processor speeds. However, they are a source of unpredictability due to their characteristi...
Xavier Vera, Björn Lisper, Jingling Xue
HPCA
2008
IEEE
15 years 10 months ago
DeCoR: A Delayed Commit and Rollback mechanism for handling inductive noise in processors
Increases in peak current draw and reductions in the operating voltages of processors continue to amplify the importance of dealing with voltage fluctuations in processors. Noise-...
Meeta Sharma Gupta, Krishna K. Rangan, Michael D. ...
ISCAS
2006
IEEE
142views Hardware» more  ISCAS 2006»
15 years 3 months ago
An efficient texture cache for programmable vertex shaders
Vertex texturing is state-of-the-art functionality of vertex. Thus, traditional texture caches used in RE are not the 3D geometry processor. However, it aggravates the always appli...
Seunghyun Cho, Chang-Hyo Yu, Lee-Sup Kim
106
Voted
TPDS
2008
150views more  TPDS 2008»
14 years 9 months ago
Mitosis: A Speculative Multithreaded Processor Based on Precomputation Slices
This paper presents the Mitosis framework, which is a combined hardware-software approach to speculative multithreading, even in the presence of frequent dependences among threads....
Carlos Madriles, Carlos García Quiño...