Sciweavers

347 search results - page 35 / 70
» Caching processor general registers
Sort
View
ISORC
2007
IEEE
15 years 4 months ago
Time-Predictable Task Preemption for Real-Time Systems with Direct-Mapped Instruction Cache
Modern processors used in embedded systems are becoming increasingly powerful, having features like caches and pipelines to speedup execution. While execution speed of embedded so...
Raimund Kirner, Peter P. Puschner
WMPI
2004
ACM
15 years 3 months ago
Understanding the effects of wrong-path memory references on processor performance
High-performance out-of-order processors spend a significant portion of their execution time on the incorrect program path even though they employ aggressive branch prediction al...
Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale ...
SIGOPS
2008
122views more  SIGOPS 2008»
14 years 9 months ago
Do commodity SMT processors need more OS research?
The availability of Simultaneous Multithreading (SMT) in commodity processors such as the Pentium 4 (P4) has raised interest among OS researchers. While earlier simulation studies...
Yaoping Ruan, Vivek S. Pai, Erich M. Nahum, John M...
129
Voted
SIGMOD
2007
ACM
121views Database» more  SIGMOD 2007»
15 years 9 months ago
EaseDB: a cache-oblivious in-memory query processor
We propose to demonstrate EaseDB, the first cache-oblivious query processor for in-memory relational query processing. The cacheoblivious notion from the theory community refers t...
Bingsheng He, Yinan Li, Qiong Luo, Dongqing Yang
ICCD
2005
IEEE
108views Hardware» more  ICCD 2005»
15 years 6 months ago
Methods for Modeling Resource Contention on Simultaneous Multithreading Processors
Simultaneous multithreading (SMT) seeks to improve the computation throughput of a processor core by sharing primary resources such as functional units, issue bandwidth, and cache...
Tipp Moseley, Dirk Grunwald, Joshua L. Kihm, Danie...