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IPPS
2007
IEEE
15 years 10 months ago
Multi-Core Model Checking with SPIN
—We present the first experimental results on the implementation of a multi-core model checking algorithm for the SPIN model checker. These algorithms specifically target shared-...
Gerard J. Holzmann, Dragan Bosnacki
ETS
2006
IEEE
113views Hardware» more  ETS 2006»
15 years 10 months ago
Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism
This paper proposes a wrapper design for interconnects with guaranteed bandwidth and latency services and on-chip protocol. strate that these interconnects abstract the interconne...
Alexandre M. Amory, Kees Goossens, Erik Jan Marini...
ISCAS
2006
IEEE
95views Hardware» more  ISCAS 2006»
15 years 10 months ago
Low-latency, HDL-synthesizable dynamic clock frequency controller with self-referenced hybrid clocking
—A low-latency, HDL-synthesizable dynamic clock frequency controller is presented as a time-efficient alternative to full-custom implementations. Frequency division of a fully in...
Robert M. Senger, Eric D. Marsman, Gordy A. Carich...
ISCAS
2006
IEEE
154views Hardware» more  ISCAS 2006»
15 years 10 months ago
FleXilicon: a reconfigurable architecture for multimedia and wireless communications
— This paper proposes a new reconfigurable architecture for multi-media and wireless communications. The proposed architecture addresses three critical design issues with the loo...
Jong-Suk Lee, Dong Sam Ha
ITNG
2006
IEEE
15 years 10 months ago
Rethinking Programming
The accepted view of programming, rooted in Turing’s fundamental characterization of algorithms, has had a profound impact on the theory and practice of computing with yet broad...
W. M. Beynon, R. C. Boyatt, S. B. Russ