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DAC
2009
ACM
15 years 4 months ago
Yield-driven iterative robust circuit optimization algorithm
This paper proposes an equation-based multi-scenario iterative robust optimization methodology for analog/mixed-signal circuits. We show that due to local circuit performance mono...
Yan Li, Vladimir Stojanovic
DAC
2003
ACM
15 years 2 months ago
Symbolic analysis of analog circuits with hard nonlinearity
A new methodology is presented to solve a strongly nonlinear circuit, characterized by Piece-Wise Linear (PWL) functions, symbolically and explicitly in terms of its circuit param...
Alicia Manthe, Zhao Li, C.-J. Richard Shi
ICCAD
2006
IEEE
208views Hardware» more  ICCAD 2006»
15 years 6 months ago
Automation in mixed-signal design: challenges and solutions in the wake of the nano era
The use of CMOS nanometer technologies at 65 nm and below will pose serious challenges on the design of mixed-signal integrated systems in the very near future. Rising design comp...
Trent McConaghy, Georges G. E. Gielen
SBCCI
2005
ACM
132views VLSI» more  SBCCI 2005»
15 years 3 months ago
Design and power optimization of CMOS RF blocks operating in the moderate inversion region
In this work the design of radiofrequency CMOS circuit blocks in the 910MHz ISM band, while biasing the MOS transistor in the moderate inversion region, is analyzed. An amplifier ...
Leonardo Barboni, Rafaella Fiorelli
126
Voted
ISPD
2012
ACM
288views Hardware» more  ISPD 2012»
13 years 5 months ago
Construction of realistic gate sizing benchmarks with known optimal solutions
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
Andrew B. Kahng, Seokhyeong Kang