170 search results - page 9 / 34 » Challenges in Embedded Memory Design and Test |
113
Voted
ICCAD
2000
IEEE
15 years 7 months ago
2000
IEEE
Spurred by technology leading to the availability of millions of gates per chip, system-level integration is evolving as a new paradigm, allowing entire systems to be built on a s...
126
Voted
ISCA
2006
IEEE
15 years 9 months ago
2006
IEEE
Long interconnects are becoming an increasingly important problem from both power and performance perspectives. This motivates designers to adopt on-chip network-based communicati...
137
Voted
IPPS
2007
IEEE
15 years 9 months ago
2007
IEEE
Code compression has been applied to embedded systems to minimize the silicon area utilized for program memories, and lower the power consumption. More recently, it has become a n...
119
Voted
DATE
2003
IEEE
15 years 8 months ago
2003
IEEE
In modern SoCs, embedded memories occupy the largest part of the chip area and include an even larger amount of active devices. As memories are designed very tightly to the limits...
145
Voted
DAC
2011
ACM
14 years 3 months ago
2011
ACM
Modern processor architectures call for software that is highly tuned to an unpredictable operating environment. Processlevel virtualization systems allow existing software to ada...