280 search results - page 3 / 56 » Challenges in exploitation of loop parallelism in embedded a... |
ICIP
2003
IEEE
14 years 7 months ago
2003
IEEE
This paper describes a new co-processor architecture designed for CMOS sensor imaging. The co-processor unit is integrated into the image acquisition loop so as to exploit the ful...
PLDI
2012
ACM
11 years 8 months ago
2012
ACM
Software-based thread-level parallelization has been widely studied for exploiting data parallelism in purely computational loops to improve program performance on multiprocessors...
ICPADS
2006
IEEE
14 years 9 days ago
2006
IEEE
One of the major factors that can potentially slow down widespread use of embedded chip multiprocessors is lack of efficient software support. In particular, automated code paral...
WOMPAT
2004
Springer
13 years 11 months ago
2004
Springer
OpenMP allows programmers to specify nested parallelism in parallel applications. In the case of scientific applications, parallel loops are the most important source of paralleli...
CODES
2005
IEEE
13 years 12 months ago
2005
IEEE
Multimedia vector instruction sets are becoming ubiquitous in most of the embedded systems used for multimedia, networking and communications. However, current compiler technology...