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ISCAPDCS
2004
15 years 3 months ago
One-Level Cache Memory Design for Scalable SMT Architectures
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past de...
Muhamed F. Mudawar, John R. Wani
JCM
2008
118views more  JCM 2008»
15 years 1 months ago
New Receiver Architecture Based on Optical Parallel Interference Cancellation for the Optical CDMA
Optical Code Division Multiple Access (OCDMA) is considered as the strongest candidates for the future high speed optical networks due to the large bandwidth offered by the system,...
N. Elfadel, A. A. Aziz, E. Idriss, A. Mohammed, N....
JSAC
2008
90views more  JSAC 2008»
15 years 1 months ago
Limited feedback schemes for downlink OFDMA based on sub-channel groups
Abstract--In a downlink Orthogonal Frequency Division Multiple Access (OFDMA) system, optimally allocating sub-channels across mobile users can require excessive feedback of channe...
Jieying Chen, Randall A. Berry, Michael L. Honig
JSAC
2008
98views more  JSAC 2008»
15 years 1 months ago
Multiuser Detection of Sparsely Spread CDMA
Code-division multiple access (CDMA) is the basis of a family of advanced air interfaces in current and future generation networks. The benefits promised by CDMA have not been full...
Dongning Guo, Chih-Chun Wang
JEC
2006
100views more  JEC 2006»
15 years 1 months ago
RC-SIMD: Reconfigurable communication SIMD architecture for image processing applications
During the last two decades, Single Instruction Multiple Data (SIMD) processors have become important architectures in embedded systems for image processing applications. The main ...
Hamed Fatemi, Bart Mesman, Henk Corporaal, Twan Ba...