Sciweavers

509 search results - page 71 / 102
» Chip Multi-Processor Generator
Sort
View
DFT
2006
IEEE
148views VLSI» more  DFT 2006»
15 years 7 months ago
Bilateral Testing of Nano-scale Fault-tolerant Circuits
As the technology enters the nano dimension, the inherent unreliability of nanoelectronics is making fault-tolerant architectures increasingly necessary in building nano systems. ...
Lei Fang, Michael S. Hsiao
ISLPED
2007
ACM
99views Hardware» more  ISLPED 2007»
15 years 6 months ago
Thermal-aware task scheduling at the system software level
Power-related issues have become important considerations in current generation microprocessor design. One of these issues is that of elevated on-chip temperatures. This has an ad...
Jeonghwan Choi, Chen-Yong Cher, Hubertus Franke, H...
ENGL
2008
100views more  ENGL 2008»
15 years 5 months ago
HIDE+: A Logic Based Hardware Development Environment
With the advent of System-On-Chip (SOC) technology, there is a pressing need to enhance the quality of ools available and increase the level of abstraction at which hardware is des...
Abdsamad Benkrid, Khaled Benkrid
TCAD
2011
14 years 12 months ago
GRIP: Global Routing via Integer Programming
Abstract—This work introduces GRIP, a global routing technique via integer programming. GRIP optimizes wirelength and via cost directly without going through a traditional layer ...
Tai-Hsuan Wu, Azadeh Davoodi, Jeffrey T. Linderoth
DAC
2006
ACM
16 years 6 months ago
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
Three-dimensional (3-D) integrated circuits have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs. While they offer several othe...
Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sh...