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71
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ASPDAC
2006
ACM
130views Hardware» more  ASPDAC 2006»
15 years 3 months ago
Convergence-provable statistical timing analysis with level-sensitive latches and feedback loops
Statistical timing analysis has been widely applied to predict the timing yield of VLSI circuits when process variations become significant. Existing statistical latch timing met...
Lizheng Zhang, Jeng-Liang Tsai, Weijen Chen, Yuhen...
DAC
2008
ACM
15 years 10 months ago
On the role of timing masking in reliable logic circuit design
Soft errors, once only of concern in memories, are beginning to affect logic as well. Determining the soft error rate (SER) of a combinational circuit involves three main masking ...
Smita Krishnaswamy, Igor L. Markov, John P. Hayes
58
Voted
DAC
2004
ACM
15 years 10 months ago
Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining
With deep-sub-micron (DSM) technology, statistical timing analysis becomes increasingly crucial to characterize signal transmission over global interconnect wires. In this paper, ...
Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
83
Voted
VLSID
2005
IEEE
150views VLSI» more  VLSID 2005»
15 years 10 months ago
Multivariate Normal Distribution Based Statistical Timing Analysis Using Global Projection and Local Expansion
This paper employs general multivariate normal distribution to develop a new efficient statistical timing analysis methodology. The paper presents the theoretical framework of the...
Baohua Wang, Pinaki Mazumder
69
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DATE
2005
IEEE
132views Hardware» more  DATE 2005»
15 years 3 months ago
Statistical Timing Analysis using Levelized Covariance Propagation
Variability in process parameters is making accurate timing analysis of nano-scale integrated circuits an extremely challenging task. In this paper, we propose a new algorithm for...
Kunhyuk Kang, Bipul Chandra Paul, Kaushik Roy