366 search results - page 25 / 74 » Circuit optimization using statistical static timing analysi... |
ISQED
2010
IEEE
15 years 6 months ago
2010
IEEE
With the CMOS transistors being scaled to sub 45nm and lower, Negative Bias Temperature Instability (NBTI) has become a major concern due to its impact on PMOS transistor aging pr...
102
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ICCAD
1998
IEEE
15 years 4 months ago
1998
IEEE
Noise can cause digital circuits to switch incorrectly and thus produce spurious results. Noise can also have adverse power, timing and reliability e ects. Dynamic logic is partic...
81
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ICCAD
1998
IEEE
15 years 4 months ago
1998
IEEE
This paper presents an efficient statistical design methodology that allows simultaneous sizing for performance and optimization for yield and robustness of analog circuits. The s...
102
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ICC
2009
IEEE
15 years 6 months ago
2009
IEEE
—We present a detection scheme for multiple-symbol DPSK for use in a statistically unknown time-varying channel. The scheme relies on a parametric representation of the timevaryi...
GLVLSI
2006
IEEE
15 years 5 months ago
2006
IEEE
Process variations have become a key concern of circuit designers because of their significant, yet hard to predict impact on performance and signal integrity of VLSI circuits. St...